1. Field of the Invention
The present invention relates to data communications circuits and, in particular, to an asynchronous communications element which is operable in alternate modes for use with a variety of CPUs and peripherals.
2. Discussion of the Prior Art
Data communications is a broad term used to define the transmission of data from one point to another.
To ensure that two or more communications stations may coherently communicate data between one another, a protocol is established to define the characteristics of the communication link.
The most popular protocol for data transmission is asynchronous communication. This protocol specifies that each data character to be transmitted be proceeded by a "start" bit and be followed by one or more "stop" bits. Between characters, a mark condition is continuously maintained. Because each transmitted character is bracketed by these "start" and "stop" bits, the receiving station is resynchronized with each transmission, allowing unequal intervals between characters.
One commonly used asynchronous data communications device is the universal asynchronous receiver/transmitter, or UART. UARTs rely on two separate serial shift registers, each with its own serial port and clock, to receive data from and transmit data to a modem or peripheral device in response to control signals from an associated central processing unit. This architecture allows full duplex operation at different data rates.
To transmit data from its associated central processing unit to a selected modem or peripheral device, a UART can request the parallel transfer of data (typically an 8-bit character which is placed on the system's data bus by the central processing unit) into the UART's transmitter holding register The transmitter holding register then transfers the data to a transmitter shift register which serially transmits each bit of data to the peripheral device. Initially, when the transmitter holding register is empty, the UART signals the central processing unit that it is ready to receive data. Data is tranferred when a data strobe input to the UART is appropriately pulsed.
Since the transmitter holding register is "empty" as soon as the parallel transfer of data to the transmitter shift register occurs, even if the actual serial shifting of data by the shift register is not complete, the UART may indicate to the central processing unit that a new data character may be loaded to the holding register. When the new data is loaded into the holding register, if the serial transmitter shift register is not yet free, the data is held in the holding register until the serial shift of the initial data is completed. The transfer of the new data into the shift register is then allowed to take place.
Thus, a typical UART can retain a maximum of two data characters for transmission from its associated central processing unit. If the full transmission requires the transfer of more than two characters, the central processing unit, which can transfer data much faster than the UART's transmitter shift register, must either wait for the register to complete its serial transfer or go to different tasks and then respond to many interrupts from the UART to complete the transmission. Both alternatives are an extremely inefficient use of central processing unit time.
Receipt of data by the central processing unit from a modem or other peripheral device via the UART is subject to the same time inefficiencies as is data transmission. That is, the central processing unit is inhibited by the operating rate and data capacity of the UART. As in data transmission, to receive data, the UART utilizes a shift register and a holding register. A data character is shifted serially from the modem or peripheral device into a serial-to-parallel receiver shift register. When the entire character has been assembled in the shift register, it is transferred to a receiver holding register, freeing the receiver shift register to receive the next character. The UART indicates it has received data ready to be transferred to the CPU and places the data on the system bus for parallel transfer when the appropriate strobe is received by the central processing unit.
UARTs are available which utilize a first-in-first-out memory to replace the receiver shift register
UARTs may be used either in an interrupt mode or in a polling configuration. In the interrupt mode, the UART sends an interrupt to the central processing unit which services it by either placing data on or retrieving data from the system bus. In the polling mode, the central processing unit periodically interrogates the UART to determine whether it is ready to send or whether it has received data.